hi im triying every digit number thing easy if cant divide 10 thing i'm working on verilog hdl there way it?
heres original code dividing number 10
`timescale 1ns / 1ps `default_nettype none module divisorde10(//16 digitos input wire [31:0]suma_total, input wire en, output wire[3:0] digito ); reg [3:0]digit; reg [31:0]num; reg [31:0]resul; @(*) begin num=suma_total; while(num!=0)begin resul=num/10; digit=num-resul*10; if(en)begin num=resul; end end end assign digito=digit; endmodule
and here's error:
line 16: operator / supported when second operand power of 2.
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