vhdl - Generic Multiplexer warning -

i created generic multiplexer( on number of inputs , bits per input) in vhdl. tested , works correctly width mismatch warning: width mismatch. < output > has width of 8 bits assigned expression 64-bit wide. code of generic mux. can explain me why warning? what's wrong code? professor wants me implement without use of process. thanks

library ieee;  use ieee.std_logic_1164.all; use work.package_log.all; use ieee.numeric_std.all;  entity mux_generic  generic(n : natural :=8;          m : natural := 8);             -- n: number of inputs             -- m: bit per input/output port ( input : in  std_logic_vector (n*m-1 downto 0);           sel: in std_logic_vector (log2ceil(n)-1 downto 0);        output : out  std_logic_vector (m-1 downto 0)); end mux_generic;  architecture dataflow of mux_generic  begin  output <= input(m*(to_integer(unsigned(sel))+1) - 1 downto m*(to_integer(unsigned(sel))));  end dataflow; 

the function log2ceil defined in way:

library ieee; use ieee.std_logic_1164.all;  package package_log      function log2ceil( n : natural) return natural;  end package_log;  package body package_log  function log2ceil (n : natural) return natural          variable i, j : natural;      begin         := 0;         j := 1;         while (j < n) loop             := i+1;             j := 2*j;         end loop;         return i;      end function log2ceil;  end package_log; 

please update lastest ise version 14.7, if haven't done far. enable new parser spartan-3e fpga:

• right click on synthesize -> process properties.
• change property display level "advanced".
• for property "other xst command line options" enter -use_new_parser yes.

now warning goes away. new warning appears, noting, new parser not default one. but, didn't experienced problem yet.

by way, multiplexer description not yet efficient. take @ @ my other post, different implementations , effects on resource usage , timing analysis.